Design of Delay-Power Efficient Carry Select Adder using 3-T XOR Gate

Abstract

In VLSI system design, the digital adders significantly affects the overall proficiency of the system. Having adders with low

cost and fast addition operation is the most desirable requirement in todays VLSI design and Carry Select Adder (CSLA) is the most

appropriate among all known adder structures. This proposed work uses a 3T XOR gate to design a 16-bit CSLA which largely reduces

the total transistor count of 16-bit CSLA as XOR gates are essential block in adders. This reduction in total transistor count helps in the

reduction of power consumption and power-delay product (PDP) with an increase in speed when compared with Modified-CSLA.